Synopsys Design Compiler Tutorial 2021 [2027]

DC parses the HDL code (Verilog/SystemVerilog/VHDL) and converts it into an internal, technology-independent intermediate format called GTECH.

exit

set target_library "tcbn28hpc.db"

write_sdc outputs/constraints_out.sdc

, which includes high-efficiency optimization engines and cloud-ready capabilities for advanced nodes The Synthesis Flow synopsys design compiler tutorial 2021

You can read your hardware description files into the DC memory using either the read_file command or the safer analyze and elaborate combination. The latter is highly recommended for modern VHDL and SystemVerilog designs.

The standard synthesis flow followed by industry teams typically involves the following steps: synopsys design compiler tutorial 2021

Or run in batch mode from the Linux shell:

create_voltage_domain -name VDD_CORE -voltage 0.8 create_voltage_domain -name VDD_IO -voltage 1.8 set_voltage 0.8 -domain VDD_CORE set_voltage 1.8 -domain VDD_IO set_level_shifter_strategy -domain VDD_CORE -from_domain VDD_CORE -to_domain VDD_IO INSERT_LEVEL_SHIFTERS synopsys design compiler tutorial 2021